module mod_a (
    input clk,
    input rst_n,

    input start_req,
    output reg captured
);

///
/// 检测 上升沿
///
wire startreq_posedge;
reg  startreq_d0;
reg  startreq_d1;

assign startreq_posedge = ~startreq_d0 & (startreq_d1);

// 两拍检测法-检测
always @ (posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        startreq_d0 <= 0;
        startreq_d1 <= 0;
    end else begin
        startreq_d0 <= start_req;
        startreq_d1 <= startreq_d0;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        captured <= 1'b0;
    end else begin
        if (startreq_posedge)
            captured <= 1'b1;
        else
            captured <= 1'b0;
    end
end

endmodule 
